{"id":78,"date":"2013-08-22T20:56:26","date_gmt":"2013-08-22T20:56:26","guid":{"rendered":"http:\/\/blogs.uakron.edu\/aspc-lab\/?page_id=78"},"modified":"2014-12-10T23:07:47","modified_gmt":"2014-12-10T23:07:47","slug":"publications","status":"publish","type":"page","link":"https:\/\/blogs.uakron.edu\/aspc-lab\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"
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Journal Articles<\/span><\/p>\n

1.\u00a0[pdf]<\/a>\u00a0A. Madanayake and L.T. Bruton, “Low-complexity distributed-parallel-processor for 2D IIR broadband beam plane-wave \u00a0filters”, Canadian Journal of Electrical and Computer Engineering (CJECE), summer 2007, vol. 32, no.3, pp.123-131.<\/p>\n

2.\u00a0[pdf]<\/a>\u00a0A. Madanayake and L.T Bruton, \u201cA Fully-multiplexed First-order Frequency-planar Module for Fan, Beam,\u00a0and Cone Plane-wave Filters\u201d, IEEE Trans. On Circuits and Systems: Express Briefs, vol. 53, issue 8, August\u00a0 2006, pp. 697-701.<\/p>\n

3.\u00a0[pdf]<\/a>\u00a0A. Madanayake and L.T. Bruton, “A Speed-optimized Systolic-array Processor Architecture for Spatio-temporal 2D IIR Broadband Beam Filters”, IEEE Trans. on Circuits and Systems-I: Regular Papers, Vol. 55, No.\u00a07, August 2008, pp. 1953-1966.<\/p>\n

4.\u00a0[pdf]\u00a0<\/a>A. Madanayake and L.T. Bruton, “A Systolic-array Architecture for First-order 3D IIR Frequency-planar\u00a0Filters”, IEEE Trans. on Circuits and Systems-I: Regular Papers, Vol. 55, No. 6, July 2008, pp. 1546-1559.<\/p>\n

5.\u00a0[pdf]<\/a>\u00a0A. Madanayake, S.V. Hum, and L.T. Bruton, \u201cA Systolic Array 2D IIR Broadband RF Beamformer\u201d, IEEE\u00a0Transactions on Circuits and Systems-II: Express Briefs, Vol. 55, No. 12, December 2008, pp. 1244-1248.<\/p>\n

6.\u00a0[pdf]<\/a>\u00a0S.V. Hum, A. Madanayake, and L.T. Bruton, \u201cUWB Beamforming using 2D Beam Digital Filters\u201d, IEEE\u00a0Transactions on Antennas and Propagation (TAP), Vol. 57, No. 3, March 2009, pp. 804-807.<\/p>\n

Journal papers at University of Akron, 2010-\u00a0<\/strong><\/p>\n

7. A. Madanayake, T.K. Gunaratne, L.T. Bruton, \u201cMassively-Parallel Systolic-Array Architectures for 2D IIR\u00a0Polyphase Space-Time Plane-Wave Beam Digital Filters\u201d, Intl. J. Circuit Theory and Applications (CTA), Wiley-Blackwell, Impact Factor = 2.011.<\/span><\/span><\/p>\n

8. A. Madanayake, S.V. Hum, and L.T. Bruton, \u201cEffects of Quantization in Systolic 2D IIR Beam Filters on UWB\u00a0Wireless Communications\u201d, Circuits, Systems, and Signal Processing (Springer). Impact Factor 0.752.<\/p>\n

9. [pdf<\/a>] A. Madanayake, T.K. Gunaratne, and L.T. Bruton,\u00a0\u201cReducing The Multiplier-Complexity of Massively\u00a0Parallel Polyphase 2D IIR Broadband Beam Filters\u201d\u00a0 is accepted for publication at Circuits, Systems and Signal\u00a0Processing (CSSP), vol. 31, pp.1229-1243. Impact Factor=0.752.<\/p>\n

10. [pdf<\/a>] N. Arbabi, M. Almalkawi, V. Devabhaktuni, M. Yagoub, and A. Madanayake, \u201cA compact realization of\u00a0composite lowpass filter for monolithic microwave integrated circuit (MMIC) applications,\u201d International\u00a0Journal of RF and Microwave Computer-Aided Engineering, vol. 22, pp. 147-152, March 2012.<\/p>\n

11. [pdf<\/a>] R.M. Joshi, A. Madanayake, L.T. Bruton and J. Adikari, “Synthesis and Array Processor Realization of a 2D IIR Beam Filter for Wireless Applications\u201d, IEEE Trans. on Very Large Scale Integration Systems, 5-year Impact Factor = 1.5, vol. 20, no. 12, pp. 2241- 2254, Dec. 2012.<\/p>\n

12.\u00a0 [pdf<\/a>] A. Madanayake, R. Cintra, N. Rajapaksha, D. Onen, V.S. Dimitrov, A. Edirisuriya and L.T. Bruton, \u201cA Row-parallel 8\u00d78 2-D DCT Architecture Using Algebraic Integer Based Exact Computation\u201d, IEEE Trans. on Circuits and Systems for Video Technology, vol. 22, no. 6, pp. 915-929,\u00a0 June 2012. 5-year Impact Factor = 3.012.<\/p>\n

13. [pdf<\/a>] C. Wijenayake, Y. Xu, A. Madanayake, L. Belostotski, L.T. Bruton,\u00a0\u201cRF Analog Beamforming Fan Filters Using CMOS All-pass Time Delay Approximations\u201d, IEEE Trans. on Circuits and Systems:-I: Regular Papers, Special Issue based on IEEE Intl. Symp. on Circuits and Systems (ISCAS\u20182011) held in Rio De Janeiro, Brazil, vol. 59, issue 5, pp. 1061-1073, May 2012.<\/p>\n

14. [pdf<\/a>] A. Madanayake, R.J. Cintra, V.S. Dimitrov and L.T. Bruton, \u201cBlock-Parallel Systolic-Array Architecture for 2-D NTT-Based Fragile Watermark Embedding\u201d, Parallel Processing Letters (PPL), vol. 22, no. 3, 12 pages, 2012.<\/p>\n

15. [pdf<\/a>] N. Rajapaksha, A. Madanayake and L.T. Bruton, \u201c2D Space-time Wave-Digital Multi-fan Filter Banks for Signals Consisting of Multiple Plane Waves\u201d, Multi-Dimensional Systems and Signal Processing (MSSP), Accepted, 2012.<\/p>\n

16. [pdf<\/a>] A. Edirisuriya, A. Madanayake, R. J. Cintra, V.S. Dimitrov, and J. Adikari, \u201cVLSI Architecture for 8-Point AI- based Arai-DCT having Low AT Complexity and Power at Improved Accuracy using 40 nm FPGA and 65 nm Standard Cells\u201d, Journal of Low Power Electronics and Applications, Special Issue on Recent Developments, vol. 2, April 2012, pp. 127-142.<\/p>\n

17. [pdf<\/a>] L.T. Bruton, A. Madanayake and C. Wijenayake, \u201cContinuous-Time Analog 2D IIR Beam Filters\u201d, IEEE Trans. on Circuits and Systems-II: Express Briefs, vol 59, issue 7, 2012, pp. 419-423.<\/p>\n

18. [pdf<\/a>] S. Kondapalli, A. Madanayake and L.T. Bruton, \u201cDigital Architectures for UWB Beamforming using 2-D IIR Spatio-temporal Frequency-Planar Filters\u201d, Hindawi International Journal of Antennas and Propagation, Special Issue on Beamforming Networks. Impact Factor=0.48, June 2012.<\/p>\n

19.\u00a0 [pdf<\/a>] C. Wijenayake, A. Madanayake and L.T. Bruton, \u201cBroadband Multiple Cone-Beam 3D IIR Digital Filters Applied to Planar Dense Aperture Arrays\u201d, IEEE Trans. on Antennas and Propagation (TAP), vol. 60, no. 11, pp. 5136-5146, Nov. 2012.<\/p>\n

20. [pdf<\/a>] F. Bayer, A. Edirisuriya, R. Cintra, and A. Madanayake,\u00a0\u201cA digital hardware fast algorithm and FPGA-based prototype for a novel 16-point approximate DCT for image compression applications\u201d, Institute of Physics (IoP) Measurement Science and Technology (MST), Special Issue on Imaging, vol. 23, 2012.<\/p>\n

21. [pdf<\/a>] S. Madishetty, A. Madanayake, R.J. Cintra, V. Dimitrov and V.S. Dimitrov, \u201cVLSI Architectures for the 4-tap and 6-tap 2-D Daubechies Wavelet Filters using Algebraic Integers\u201d, IEEE Trans. on Circuits and Systems-I:Regular Papers, 2012, Accepted.<\/p>\n

22. [pdf<\/a>] U. Potluri, A. Madanayake, R. Cintra, F. Bayer, \u201cMultiplier-free DCT approximations for RF multi-beam digital\u00a0aperture-array space imaging and directional sensing\u201d, IoP Measurement Science and Technology (MST), Special Issue on Imaging, vol 23, 2012.<\/p>\n

23. [pdf<\/a>] L. Belostotski, A. Madanayake and L.T. Bruton, \u201cWideband LNA with Active -C Element\u201d, IEEE Microwave and Wireless Components Letters, vol 22, issue 10, Oct. 2012, pp. 524-526.<\/p>\n

24. [pdf<\/a>] A. Madanayake, C. Wijenayake, D. Dansereau, T.K. Gunaratne, L.T. Bruton, and S. Williams, “Multidimensional (MD) Circuits and Systems For Emerging Applications Including Cognitive Radio, Radio Astronomy, Robot Vision and Imaging\u201d, IEEE Circuits and Systems Society Magazine, First Quarter, 2012.<\/p>\n

25. N. Rajapaksha, A. Edirisuriya, A. Madanayake, R. Cintra, D. Onen, I. Amer and V. S. Dimitrov,\u00a0\u201cAsynchronous Realization of Algebraic Integer based 2-D DCT using Achronix Speedster SPD60 FPGA\u201d, Hindawi Journal of Electrical and Computer Engineering Special Issue on Hardware Implementation of DSP Algorithms, Accepted.<\/p>\n

26. R. Wimalagunaratne, C. Wijenayake, A. Madanayake, D. Dansereau, and L.T. Bruton, \u201cIntegral Form 4-D Light Field Filters using Xilinx FPGAs and 45 nm CMOS Technology\u201d, Multidimensional Systems and Signal Processing, Accepted.<\/p>\n

27. J. Adams, A. Madanayake and L.T. Bruton, \u201cApproximate Realization of Fractional-Order 2-D IIR Frequency- Planar Filters\u201d, IEEE Journal of Emerging and Selected Topics in Circuits and Systems (JETCAS) Special Issue on Fractional Order Systems, Accepted.<\/p>\n

28. A. Edirisuriya, N. Rajapaksha, A. Madanayake, and V.S. Dimitrov, \u201cA Single-Channel Architecture for Algebraic Integer Based 8\u00d78 2-D DCT Computation\u201d, IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), Accepted.<\/p>\n

29. \u00a0A. Madanayake, R. Wimalagunaratne, D. Dansereau, R.J. Cintra and L.T. Bruton, \u201cThe paper \u201cVLSI Architecture for 4D Depth Filtering\u201d, Signal, Image and Video Processing, Accepted.<\/p>\n

30. S. Madhishetty, A. Madanayake, R.J. Cintra, D. Mugler and V.S. Dimitrov, \u201cAlgebraic Integer Architecture With Minimum Adder Count for the 2-D Daubechies 4-tap Filters Banks\u201d, Multidimensional Systems and Signal Processing (MSSP), Accepted.<\/p>\n

31. J.Kota, C. Wijenayake, A. Madanayake, L. Belostotski and L.T. Bruton, \u201cA 2-D Signal Processing Model to Predict the Effect of Mutual Coupling on Array Factor\u201d, IEEE Antennas and Wireless Propagation Letters (AWPL), Accepted.<\/p>\n

32.\u00a0A. Madanayake, C. Wijenayake, J.S. Kota and L.T. Bruton, \u201cSpace-Time Spectral White Spaces in Cognitive Radio: Theory, Algorithms and Circuits\u201d, IEEE JETCAS Special Issue on Cognitive\/Software-Defined Radio, Accepted.<\/p>\n

33.\u00a0 A. Madanayake, C. Wijenayake, R.M. Joshi, L. Belostotski, M. Almalkawi, L.T. Bruton and V. Devabhaktuni, “Electronically Scanned RF-to-Bits Beam Aperture Arrays Using 2-D IIR Spatially Bandpass Digital Filters\u201d, Multi-Dimensional Systems and Signal Processing (MSSP), Special Issue on ND-applications, Accepted.<\/p>\n

34.\u00a0U. Potluri, A. Madanayake, R.J. Cintra, F. Bayer, A. Edirisuriya and S. Kulasekera, “Improved 8-Point\u00a0Approximate DCT for Image and Video Compression Requiring Only 14 Additions”, IEEE Trans. on\u00a0Circuits and Systems-I:Regular Papers, In press.<\/p>\n

35.\u00a0F. Bayer, R.J. Cintra, A. Madanayake and U. Potluri, “Multiplierless Approximate 4-point DCT VLSI\u00a0Architectures for Transform Block” , <\/i>IET Electronics Letters, In press.<\/p>\n

36.\u00a0S. Madhishetty, A. Madanayake, R. J. Cintra, and V. S. Dimitrov, “Precise VLSI Architecture for AI\u00a0based 1-D\/2-D Daub-6 Wavelet Filter banks with Low Adder-Count”, IEEE Trans. on CAS-I:Regular\u00a0Papers, Accepted.<\/p>\n

37. C. Wijenayake, A. Madanayake, L. Belostotski, Y. Xu and L.T. Bruton,
\n“All-Pass Filter-Based 2-D IIR Filter-Enhanced Beamformers for AESA Receivers”,\u00a0IEEE Trans. on CAS-I:Regular Papers, Special Issue on ISCAS’2013, Accepted.<\/p>\n

38. A. Madanayake, S. Wijeratne, C. Wijenayake, R. Acosta and S.I. Hariharan, “2D-IIR Time-Delay-Sum Linear Aperture Arrays”, IEEE Antennas and Propagation Letters (AWPL), 2014, Accepted.<\/p>\n

39. A. Madanayake, R.J. Cintra, F. Bayer, V.S. Dimitrov, K. Wahid, N. Rajapaksha, S. Kulasekara, A. Edirisuriya, S. Madhishetty, and U. Potluri,\u00a0\u201cLow-Power VLSI Architectures for DCT\/DWT: Precision vs Approximation for HD Video, Biomedical, and Smart Antenna Applications\u201d, IEEE Circuits and Systems Magazine, Accepted.\u00a0<\/span><\/p>\n

40.\u00a0Thiago L. T. da Silveira,\u00a0Fabio M. Bayer, Renato J. Cintra, \u00a0Sunera Kulasekera, Arjuna Madanayake, and \u00a0Alice J. Kozakevicius, “An orthogonal 16-point approximate DCT for image\u00a0and video compression”, Multidimensional Systems and Signal Processing (MSSP). Springer, Accepted.<\/p>\n

41. Nilanka Rajapaksha, Arjuna Madanayake, Leonard T. Bruton, Systolic-Array Architecture for Steer- able Multi-Beam VHF Wave-Digital RF Apertures, IEEE Transactions on Aerospace and Electronic Systems, 2014, Accepted.<\/p>\n

42. P. Ahmadi, M. Taghavi, L. Belostotski and A. Madanayake,\u00a0A 0.13-\u03bcm CMOS Current-Mode All-Pass Filter for Multi-GHz Operation, IEEE Trans. on VLSI Systems, Accepted.<\/span><\/p>\n

43.\u00a0Paulo Oliveira, Renato Cintra, Fabio Bayer, \u00a0Sunera Kulasekara, and Arjuna Madanayake, A Discrete Tchebichef Transform Approximation for Image and Video Coding, at IEEE Signal Processing Letters (SPL), Accepted.<\/span><\/p>\n

44. Dora Suarez, Fabio Bayer, Renato Cintra, Arjuna Madanayake and Sunera Kulasekara,\u00a0Multi-Beam RF Aperture using Multiplierless FFT Approximation,\u00a0<\/em>IET Electronics Letters, Accepted.<\/span><\/p>\n

45. Nilanka Rajapaksha, Arjuna Madanayake, Renato Cintra, Vassil Dimitrov, and Jithra Adikari,\u00a0VLSI Computational Architectures for the Arithmetic Cosine Transform, IEEE Trans. on Computers, Accepted.\u00a0<\/span><\/p>\n

Book Chapters<\/span><\/p>\n

1.\u00a0[pdf]<\/a>\u00a0A. Madanayake and L.T. Bruton, “The Design and FPGA-based Verification of Radio-Frequency (RF),\u00a0Beamforming Systolic Digital Filter Architectures using Two-dimensional (2D) IIR Space-time Filters”, Invited\u00a0chapter in “VLSI”, IN-TECH open access publications, Austria.<\/p>\n

Conference Papers<\/span><\/p>\n

1.\u00a0[pdf]<\/a>\u00a0A. Madanayake*, L.T. Bruton, and C.J. Comis, \u201cFPGA Architectures for Real-time 2D\/3D FIR\/IIR Plane-wave Filters\u201d, IEEE 2004 Intl. Symp. On Circuits and Systems, ISCAS\u201904, Vancouver, Canada, vol. 2, pp.\u00a0613-616, May 2004 [Poster].<\/p>\n

2.\u00a0[pdf]<\/a>\u00a0A. Madanayake* and L.T. Bruton, \u201cFully-multiplexed First-order 3D IIR Frequency-planar Filter Module\u201d,\u00a0IEEE 2006 Asia Pacific Conference on Circuits and Systems, APCCAS\u201906, Singapore, pp. 1224-1227,\u00a0December 2006.<\/p>\n

3.\u00a0[pdf]<\/a>\u00a0A. Madanayake* and L.T. Bruton, \u201cA Single-chip FPGA Architecture for 3D IIR Broadband Spatio-temporal\u00a0Beam Plane-wave Filters\u201d, IEEE 2006 Intl. Symp. On Circuits and Systems, ISCAS\u201906, Kos Island, Greece, pp.\u00a04927-4930, May 2006.<\/p>\n

4.\u00a0[pdf]<\/a>\u00a0A. Madanayake* and L.T. Bruton, \u201cCircular Array Based 2D Recursive Filtering using a Spatio-temporal\u00a0Helix Transform\u201d,IEEE 2006 Intl. Symp. On Circuits and Systems, ISCAS\u201906, Kos Island, Greece, pp.\u00a04919-4922, May 2006.<\/p>\n

5.\u00a0[pdf]<\/a>\u00a0A. Madanayake* and L.T. Bruton, \u201cA Low-complexity Scanned-array 3D IIR Frequency-planar Filter\u201d, IEEE\u00a02005 Intl. Symp. On Circuits and Systems, ISCAS\u201905, Kobe, Japan, vol.3, pp. 2032-2035, May 2005.<\/p>\n

6.\u00a0[pdf]<\/a>\u00a0A. Madanayake* and L.T. Bruton, \u201cA High-performance Distributed-parallel-processor Architecture for 3D\u00a0IIR Digital Filters\u201d,IEEE 2005 Intl. Symp. On Circuits and Systems, ISCAS\u201905, Kobe, Japan, vol. 2, pp.\u00a01457-1460, May 2005.<\/p>\n

7.\u00a0[pdf]<\/a>\u00a0A. Madanayake* and L.T. Bruton, \u201cA Review of 2D\/3D IIR Plane-wave Real-time Digital Filter Circuits\u201d,\u00a0IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2005, Saskatoon, Canada, pp.\u00a01935-1941, May 2005 [Poster].<\/p>\n

8.\u00a0[pdf]<\/a>\u00a0A. Madanayake and L.T. Bruton, \u201cOn The Design and FPGA Implementation of Real-time Scanned-array\u00a02D Frequency-planar Beam Filters\u201d, European Association for Signal Processing, EUSIPCO\u20192004, Vienna,\u00a0Austria, pp. 2011-2014, September 2004.<\/p>\n

9.\u00a0[pdf]<\/a>\u00a0A. Madanayake, S.V. Hum, and L.T. Bruton, \u201cUWB Beamforming Using Digital 2D Frequency-planar\u00a0Filters\u201d, IEEE Antennas and Propagation Symposium 2008, San Diego, July 2008.<\/p>\n

10.\u00a0[pdf]<\/a>\u00a0A. Madanayake* and L.T. Bruton, A Real-time Systolic Array Implementation of Two-dimensional IIR\u00a0Filters for Smart Antenna Array Applications, IEEE 2008 Intl. Symp. on Circuits and Systems (ISCAS\u20192008),\u00a0Seattle, pp.1252-1255, May 2008.<\/p>\n

11.\u00a0[pdf]<\/a>\u00a0A. Madanayake* and L.T. Bruton, Selective Enhancement of Space-time Broadband Spiral-waves using\u00a02D IIR Digital Filters, IEEE 2008 Intl. Symp. on Circuits and Systems (ISCAS\u20192008), Seattle, pp. 696-699, May\u00a02008.<\/p>\n

12.\u00a0[pdf]<\/a>\u00a0A. Madanayake* and L. Bruton, \u201cDigital Filtering of Toroidal Sensor-array Signals using 3D IIR\u00a0Frequency-planar Digital Filters\u201d, IEEE North East Workshop on Circuits and Systems (NEWCAS) Midwest\u00a0Symposium on Circuits and Systems (MWSCAS) 2007, Montreal, Canada, pp. 598-601, August 2007.<\/p>\n

13.\u00a0[pdf]<\/a>\u00a0A. Madanayake* and L.T. Bruton, \u201cTime-multiplexed Systolic-array Processors for Real-time 2D IIR Beam\u00a0Plane-wave Filters\u201d, IEEE North East Workshop on Circuits and Systems (NEWCAS)\/Midwest Symposium on\u00a0Circuits and Systems (MWSCAS) 2007, Montreal, Canada, pp. 686-689, August 2007.<\/p>\n

14.\u00a0[pdf]<\/a>\u00a0A. Madanayake* and L.T. Bruton, \u201cFPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam\u00a0Planewave Filters\u201d, IEEE 2006 Asia Pacific Conference on Circuits and Systems, APCCAS\u201906, Singapore, pp.\u00a0542-545, December 2006.<\/p>\n

15.\u00a0[pdf]<\/a>\u00a0A. Madanayake, T.K. Gunaratne, and L.T. Bruton, \u201cHigh Frequency Systolic Broadband Beamforming\u00a0Using Polyphase 3D IIR Frequency-planar Digital Filters with Interleaved A\/D Sampling\u201d, IEEE International\u00a0Symposium on Circuits and Systems (ISCAS\u20192009), Taiwan.<\/p>\n

16.\u00a0[pdf]<\/a>\u00a0T.K. Gunaratne*, A. Madanayake, and L.T. Bruton, \u201cAn FPGA Architecture for Real-time Polyphase 2D FIR Double Trapezoidal Plane-wave Filters\u201d, Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS\u20192008), December 2008, pp. 984-987.<\/p>\n

17.\u00a0[pdf]<\/a>\u00a0A. Madanayake and L.T. Bruton, \u201cSystolic Array Processors for 2D IIR Spatio-Temporal Beamforming \u00a0Wave-Digital Filters (WDFs)\u201d, IEEE PACRIM\u20182009, Victoria, BC, Canada.<\/p>\n

18. [pdf] A. Madanayake and L.T. Bruton, \u201cMultidimensional Raster-Scanned LC-Ladder Wave-Digital Filter\u00a0Hardware For Directional Filtering in Space-Time\u201d, IEEE International Symposium on Circuits and Systems\u00a0(ISCAS\u20192010), Paris, France,May 2010.<\/p>\n

19. [pdf] A. Madanayake and L.T. Bruton, \u201cSystolic-Array 3D Wave-Digital Beam Filters<\/a>\u201d, IEEE 2010 Asia Pacific\u00a0Conference on Circuits and Systems (APCCAS\u20192010), Malaysia, December 2010 [accepted].<\/p>\n

20. [pdf] N. Ganganath, P. Illangakoon, G. Attanayake, T. Yapa Bandara, A. Madanayake, R. Rodrigo, and\u00a0L.T.\u00a0 Bruton, \u201cScanned-Array Audio Beamforming using 2nd\u00a0and 3rd\u00a0order 2D IIR Beam Filters on FPGA\u201d,\u00a0IEEE International Conference on Microelectronics (ICM\u20192010), Cairo, Egypt, December 2010.<\/p>\n

21. [pdf] N. Rajapaksha, A. Madanayake, and L.T. Bruton, \u201cRaster-Scanned Wave-Digital Filter Architectures\u00a0for Multi-Beam 2D IIR Broadband Beamforming\u201d, IEEE International Conference on Microelectronics\u00a0(ICM\u20192010), Cairo, Egypt, December 2010.<\/p>\n

22. [pdf<\/a>] A. Madanayake, C. Wijenayake, N. Rajapaksha, R. M. Joshi, A. Chassot, E. Matas, and L.T. Bruton,\u00a0\u201cMultidimensional-DSP Algorithms and Hardware Architectures for Widefield Aperture-Arrays Aimed at\u00a0The Square Kilometer Array (SKA) Project\u201d, Department of Electronic and Telecommunication\u00a0Engineering, University of Moratuwa, Sri Lanka, Volume II, Part VII, August 2010, pp. 2-8 [Invited Paper].<\/p>\n

23. [pdf] C. Wijenayake, A. Madanayake, L.T. Bruton, “Systolic Array Architecture for 2D IIR Wideband Dual-Beam Space-Time Plane-Wave Filters”, IEEE MidWest Symposium on Circuits and Systems\u00a0(MWSCAS\u2019 2010), August 2010.<\/p>\n

24. [pdf] C. Wijenayake, A. Madanayake, L.T. Bruton, \u201cFPGA Prototypes of Differential-Form 2D-IIR Systolic Array DSP Architectures for Multi-Beam Plane-Wave Filters\u201d, IEEE SIPS Workshop, 2010, to be held in September 2010 in California.<\/p>\n

25. Chamith Wijenayake, Arjuna Madanayake, Leonid Belostotski, and Len T. Bruton, \u201cRecent Progress on Analog\/Digital VLSI 2D Filter Circuits For Beamforming Antenna Arrays\u201d, IEEE nD-S, Pointeres, France,\u00a0September 2011.<\/p>\n

26. Rimesh M. Joshi, Arjuna Madanayake, Len T. Bruton, and Mona Maini, \u201cDiscrete-Space Continuous-Time Analog Circuits for Spatially-Bandpass 2D IIR Beam Filters\u201d, IEEE nD-S, Pointeres, France,\u00a0September 2011.<\/p>\n

27.\u00a0 Leonid Belostotski, Arjuna Madanayake, Michael Petursson, and Len Bruton, \u201cModeling The Effects of\u00a0Electromagnetic Inter-Element Coupling in Broadband Antenna Arrays using Multidimensional DSP\u201d,\u00a0IEEE nD-S, Pointeres, France, September 2011.<\/p>\n

28.\u00a0 A. Madanayake, C. Wijenayake, N. Rajapaksha, K.-S. Lee, L. Belostotski, and L.T. Bruton, \u201cA New Class\u00a0of Spatially-Discrete Time-Continuous 2D IIR Filters Based on Wave-Digital-Filter Theory\u201d, IEEE 2011\u00a0Pacific Rim Conference on Circuits, Signal Processing, and Computers (PACRIM\u20192011), Victoria,\u00a0Canada, August 2011.<\/p>\n

29. Arjuna Madanayake, Dale Mugler, and Nilanka Rajapaksha, \u201cAn Asynchronous Array Architecture for\u00a016×1 DCT-4\/DST-4 on a 65nm Achronix SDP60 FPGA\u201d, IEEE MWSCAS\u20192011, August 2011.<\/p>\n

30. Amila Edirisuriya, Arjuna Madanayake, Jithra Adikari, and Vassil Dimitrov, \u201cAn Architecture for a 7×7-bit\u00a0Multiple-Radix Multiplier Building Block\u201d, IEEE MWSCAS\u20192011, August 2011.<\/p>\n

31.\u00a0 Rimesh M. Joshi, Arjuna Madanayake, and Len Bruton, \u201cA 2D IIR Spatially-Bandpass Antenna\u00a0Beamformer on a 65nm Achronix SPD60 FPGA\u201d, IEEE MWSCAS\u20192011, August 2011.<\/p>\n

32.\u00a0 Arjuna Madanayake, Randeel Wimalagunaratne, Donald Dansereau, and Len Bruton, \u201cDesign and\u00a0FPGA-Implementation of 1st-Order 4D IIR Frequency-Hyperplanar Digital Filters\u201d, IEEE MWSCAS\u20192011,\u00a0August 2011.<\/p>\n

33.\u00a0 N. Rajapaksha, A. Madanayake, and L.T. Bruton, \u201cElementary Concepts in 2D IIR Wave-Digital Filter\u00a0Design for Space-Time Array Processing\u201d, Department of Electronic and Telecommunications, University\u00a0of Moratuwa, Sri Lanka, July 2011 [Invited Paper].<\/p>\n

34. A. Madanayake, R. Cintra, D. Onen, V.S. Dimitrov, and L.T. Bruton, \u201cAlgebraic Integer based 8×8 2-D\u00a0DCT Architecture for Digital Video Processing\u201d, IEEE 2011 Intl. Symp. on Circuits and Systems\u00a0(ISCAS\u20192011), Rio, Brazil, May 2011.<\/p>\n

35.\u00a0 A. Madanayake, H.R. Bahrami, L. T. Bruton, \u201cAntenna-Array 2D-IIR Digital Filters for Carrier-Modulated\u00a0Frequency-Agile and Cognitive Wireless Systems\u201d, IEEE Intl. Symp. On Circuits and Systems\u00a0(ISCAS\u20192011), Rio, Brazil, May\u20182011.<\/p>\n

36.\u00a0 N. Rajapaksha and A. Madanayake, \u201cAsynchronous-QDI 2D IIR Digital Filter Circuits\u201d, IEEE Intl. Symp.\u00a0On Circuits and Systems (ISCAS\u20192011), Rio, Brazil, May 2011.<\/p>\n

37.\u00a0 A. Madanayake, L. Belostotski, C. Wijenayake, and L.T. Bruton, \u201cAnalog 2D Fan Filters from Discrete\u00a0Domain Transfer Functions\u201d, IEEE Intl. Symp. On Circuits and Systems (ISCAS\u20192011), Rio, Brazil, May\u00a02011.<\/p>\n

38. Arjuna Madanayake, Chamith Wijenayake, Rimesh Man Joshi, Jay Adams, Jim Grover, Joan Carletta, Tom Hartley, and Tokunbo Ogunfunmi,\u00a0\u00a0“Teaching Freshmen VHDL-Based Digital Design”, IEEE Intl. Symp. on Circuits and Systems (ISCAS\u20182012), Soul, Korea.<\/p>\n

39. Arjuna Madanayake and Len T. Bruton,\u00a0\u201cA Combined Approach to Research and Graduate-Level Teaching of Multidimensional Signal Processing, Circuits and Systems\u201d with Len Bruton,\u00a0IEEE Intl. Symp. on Circuits and Systems (ISCAS\u20182012), Seoul, Korea.<\/p>\n

40. Shiva Madhishetty, Arjuna Madanayake, Renato Cintra, Vassil Dimitrov and Dale Mugler, \u201cError-Free VLSI Architecture for the 2-D Daubechies 4-Tap Filter Using Algebraic Integers\u201d, IEEE Intl. Symp. on Circuits and Systems (ISCAS\u20182012), Seoul, Korea.<\/p>\n

41. Randeel wimalagunaratne, Arjuna Madanayake, Don Dansereau, and Len Bruton,\u201cA Systolic-Array Architecture for First-Order 4-D IIR Frequency-Planar Digital Filters\u201d, IEEE Intl. Symp. on Circuits and Systems (ISCAS\u20182012), Seoul, Korea.<\/p>\n

42. Chamith Wijenayake, Arjuna Madanayake, Yongshend Xu, Leo Belostotski and Len T. Bruton, \u201cDiscrete Space Continuous Time 2D Delay Block Using 2D All-Pass Frequency Planar Networks\u201d, IEEE Intl. Symp. on Circuits and Systems (ISCAS\u20182012), Seoul, Korea.<\/p>\n

43. Arjuna Madanayake, Chamith Wijenayake, Nghi Tran, Sean Hum, Len Bruton and Todor Cooklev, \u201cDirectional Spectrum Sensing using Tunable Multi-D Space-Time Discrete Filters\u201d, IEEE CORAL 2012.<\/p>\n

44.\u00a0\u00a0John Kota, Dezarae Holman, Eric Matas, Kyle Wilson, Arjuna Madanayake and Malik Elbuluk,\u00a0\u201cHigh-Voltage Class-D Direct-Drive Audio Amplifier for Electrostatic Loudspeakers\u201d, IEEE MidWest Symposium on Circuits and Systems (MWSCAS\u20182012), August 2012, \u00a0Best Student Paper Award<\/span>.<\/strong><\/p>\n<\/div>\n

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 <\/p>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

Journal Articles 1.\u00a0[pdf]\u00a0A. Madanayake and L.T. Bruton, “Low-complexity distributed-parallel-processor for 2D IIR broadband beam plane-wave \u00a0filters”, Canadian Journal of Electrical and Computer Engineering (CJECE), summer 2007, vol. 32, no.3, pp.123-131. 2.\u00a0[pdf]\u00a0A. Madanayake and L.T Bruton, \u201cA Fully-multiplexed First-order Frequency-planar Module for Fan, Beam,\u00a0and Cone Plane-wave Filters\u201d, IEEE Trans. On Circuits and Systems: Express Briefs, vol. […]<\/p>\n","protected":false},"author":1586,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"open","ping_status":"open","template":"","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"class_list":["post-78","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/blogs.uakron.edu\/aspc-lab\/wp-json\/wp\/v2\/pages\/78","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.uakron.edu\/aspc-lab\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/blogs.uakron.edu\/aspc-lab\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.uakron.edu\/aspc-lab\/wp-json\/wp\/v2\/users\/1586"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.uakron.edu\/aspc-lab\/wp-json\/wp\/v2\/comments?post=78"}],"version-history":[{"count":19,"href":"https:\/\/blogs.uakron.edu\/aspc-lab\/wp-json\/wp\/v2\/pages\/78\/revisions"}],"predecessor-version":[{"id":1774,"href":"https:\/\/blogs.uakron.edu\/aspc-lab\/wp-json\/wp\/v2\/pages\/78\/revisions\/1774"}],"wp:attachment":[{"href":"https:\/\/blogs.uakron.edu\/aspc-lab\/wp-json\/wp\/v2\/media?parent=78"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}