Research

We engage in 100% academic research leading to peer reviewed publications  in high quality conferences and journals.

Our primary area of interest is the design of real-time digital hardware processor architectures for spatio-temporal multidimensional signal processing (MDSP).  Spatio-temporal MDSP refers to array processing for multidimensional linear space-time invariant systems.

Our research spans  broad topics including digital and analog MD filter theory including 2D/3D and 4D filters, fast algorithms and hardware architectures, mixed-domain  systems, mixed-signal circuits, FPGA and embedded systems, FPGA-based rapid prototyping of MDSP ASICs, radio-frequency (RF) MDSP using massively-parallel systolic-array architectures, wave-digital filters for RF and multimedia systems, video processing, digital audio beamforming, radio-astronomy space imaging, and 2D/3D signal processing for high-speed wireless communications.

Our current and previous research includes

1. Basic science in 2D/3D digital filter design and digital FPGA/VLSI implementation

2. Basic science in 2D/3D wave-digital filters, 2D/3D FIR/IIR filters, speed
optimization, and quantization noise analysis.

3. Basic science in 2D/3D spatio-temporal IIR filters operating on curvilinear sensor-
arrays.

4. Digital smart antenna array 2D/3D signal processing aimed at ultra-wideband beamforming for DoD applications and cognitive radio.

For more information on our research, please contact Dr. Madanayake or consult our publications.

General information and public outreach is via our blog www.aspcgroup.net

Spatio-temporal plane-wave filters

Plane-wave filters are a MDSP method for broadband sensor-array beamforming that exploits the nature of broadband propagating waves in the 2D/3D spatio-temporal frequency-domain. We show below an example of a plane-wave in space-space (Fig.a), and as observed in 2D spacetime (x,ct) (Fig.b), followed by the non-aliased 2D spectrum (Fig.C) and partially-aliased spectrum (Fig.D) respectively. Our plane-wave filters are broadband and highly-selective and consist, in the simplest case, a beam shaped passband as shown in the below figures, that enable the extraction of signal energy based on beam orientation.

 

 

Real-time implementation of 2D/3D spatio-temporal beam filters are proposed using massively-parallel systolic-array digital VLSI architectures. Our research on digital circuits is facilitated by EDA tools and equipment from Xilinx, Mathworks, Nallatech and Achronix Semiconductor.

We hope to extend our capabilities to Altera, Cadence and Synopsys tools in the near future. We use a mixture of VHDL, model-based design, and Verilog in our digital designs which are primarily targeted at Xilinx FPGA technology.

Digital RF Aperture-Array Research Program for SKA, Radar, and Space Imaging Science

This work includes the design and simulation of three dimensional (3D) infinite impulse response (IIR) cone filterbanks which can synthesize an electronically steerable, frequency-invariant, multiple-beam array pattern for ultra wide band (UWB) smart antenna arrays. Such multi-cone UWB beamforming is a primary requirement of emerging radio astronomy and wireless communication applications. A typical setup of the proposed 3D cone filterbank and associated RF/mixed-signal circuits is shown below.

 

The 3D cone beams are obtained by cascading 3D frequency-planar filters such that they intersect in spatio-temporal frequency domain along the desired DOA. Some examples are shown below.

 

The 3D IIR filter coefficients of these frequency-planar and frequency-beam filters are expressed in closed form expressions as functions of the DOAs of the plane waves to be extracted. This provides the electronically steerable feature. Above mentioned 3D IIR digital filters are combined in a special way (in a filter bank configuration) to obtain the cone-shaped filter passbands in 3D frequency domain.  See the publication page for details.

These building block 3D IIR filters are implemented in reconfigurable digital hardware using massively parallel systolic array architectures.

Reconfigurable Embedded Digital Antenna Array Beamforming for Cognitive Radio and Cooperative Networks

DSP-based smart antenna arrays have applications in UWB wireless communications, cognitive radio, cooperative wireless sensor networks, and radar, which requires highly-directional and steerable smart antenna arrays capable of selective enhancement of spatio-temporal broadband RF plane-waves. Wireless applications also require improvement on the bit-error-rate caused due to multi-user interference and multipath fading.

The antenna arrays used for directional filtering of plane-waves employ beamforming using analog VLSI time delay networks, fractional delay based delay-and-sum digital networks, digital phased array feeds and multi-dimensional finite/infinite impulse response (FIR/IIR) digital filters. Digital IIR filters are free from fractional delays and have lower computational complexity compared to conventional delay-and-sum beamformers and also have lower circuit complexity compared to its FIR counterparts, for a given directional selectivity.

 

Our work involves the investigation of innovative 2D IIR temporally-broadband bandpass digital beam filters. New hardware implementations are proposed and improvement of bit-error-rate performance is investigated. The proposed filters are capable of high-speed filtering of partially-broadband carrier modulated spatio-temporal plane-waves based on their DOAs, making them well-suited for wireless applications.

The lower computational complexity, closed-form design approach, broadband performance, electronic steerability, and availability of rapid reconfigurable programming logic realizations make these emerging 2D spatio-temporal digital filters very attractive and promising for cognitive radio applications. These 2D IIR filters are practical-BIBO stable having both spatial and temporal recursion in their difference equation, allowing a massively-parallel systolic-array architecture for real-time VLSI implementations.

The systolic-array architecture consists of arrays of identical interconnected processors and are highly modular and regular, making it suitable for VLSI realizations and high-speed applications. A typical 2D magnitude frequency response of the IIR bandpass beam filter is shown for the ideal case (infinite array) on the left, and for a real-world ULA having 9 antennas, on the right.

 

 

 

Recent results (with our collaboarators,  Hamid Bahrami and Len Bruton) show the simulated improvement in BER vs. SIR of about 15 dB for narrowband BPSK wireless communications.

In addition to narrowand BPSK, we simulated, using computational electromagnetic modeling, the BER vs. SIR performance of 2D IIR beam filters for UWB wireless communications. The radio propagation inside a realistic model of a typical office building was simulated using GPU accelerated FDTD code.  This work was done in collaboration with Dr Sean Hum and Dr Len Bruton. We also studied the degradation of BER vs. SIR in the presence of quantization noise inside fixed-point massively-parallel systolic-array VLSI hardware.

Other topics include hardware architectures for DCT and wavelet transforms, fast algorithms for approximating the DCT operation, number-theoretic watermarking,  4D light-fields, and digital multipliers of cryptographic size. Our group also conducts research high-speed digital architectures using clock-free asynchronous quasi delay insensitive (a-QDI) logic using Achronix FPGA devices.   

At present,  our work does not include deliverables such as designs, prototypes or software code to federal agencies, defense contractors or other companies. All EDA tools obtained at academic prices will only be used for generating scholarly articles and conference presentations.

Equipment

 

 

 

 

 

Achronix Speedster Asynchronous FPGA board.

Xilinx XtremeDSP Kit-4 (not shown)

 

Technology Links

 

Xilinx
Achronix
Tierlogic
Synopsys
Mentor Graphics
Altera
Cadence
Nallatech
LyrTech
Impulse Accelerated
AccelerEyes